A 7 bit, 3.75 ps Resolution Two-Step Time-to-Digital Converter in 65 nm CMOS Using Pulse-Train Time Amplifier

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In this paper, a novel pulse-train time amplifier is proposed that achieves linear, accurate, and programmable gain for a wide input range. Using the proposed pulse-train time amplifier, a 7-bit two-step TDC is implemented. The proposed TDC employs repetitive pulses with gated delay-lines for a calibration-free and programmable time amplification and quantization. The prototype chip fabricated in 65 nm CMOS process achieves 3.75 ps of time resolution at 200 MS/s while consuming 3.6 mW and occupying 0.02 mm(2) area. Compared to previously reported TDCs, the proposed TDC achieves the fastest conversion rate and the best FoM without any calibration.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2013-04
Language
English
Article Type
Article; Proceedings Paper
Keywords

DELAY-LINE; TDC

Citation

IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.48, pp.1009 - 1017

ISSN
0018-9200
DOI
10.1109/JSSC.2013.2237996
URI
http://hdl.handle.net/10203/191228
Appears in Collection
EE-Journal Papers(저널논문)
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