DC Field | Value | Language |
---|---|---|
dc.contributor.author | Kim, Dong-Oh | ko |
dc.contributor.author | Moon, Dong-Il | ko |
dc.contributor.author | Choi, Yang-Kyu | ko |
dc.date.accessioned | 2014-09-04T08:46:21Z | - |
dc.date.available | 2014-09-04T08:46:21Z | - |
dc.date.created | 2014-03-25 | - |
dc.date.created | 2014-03-25 | - |
dc.date.issued | 2014-02 | - |
dc.identifier.citation | IEEE ELECTRON DEVICE LETTERS, v.35, no.2, pp.220 - 222 | - |
dc.identifier.issn | 0741-3106 | - |
dc.identifier.uri | http://hdl.handle.net/10203/190190 | - |
dc.description.abstract | The long-term endurance characteristics are investigated for MOSFET-based capacitorless one-transistor DRAM (1T-DRAM) under the conventional versus biristor mode. Based on the experimental results and on a supporting simulation study, it was found that the MOSFET-based 1T-DRAM, when enabled by a biristor mode, is preferred for long-term endurance compared with MOSFET-based 1T-DRAM when operated in a conventional mode. Although a high drain voltage is required in the biristor mode for programming, improved endurance characteristics are observed. The simulation study showed that this feature is achieved by the suppression of hot-hole-induced degradation, which arises from the absence of a gate use at the dynamic cell. Thus, this letter provides a new type of device architecture as well as a novel and innovative operational method pertaining to conventional 1T-DRAM to mitigate the problem of limited endurance. | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.subject | DEVICE | - |
dc.subject | RAM | - |
dc.title | Optimization of Bias Schemes for Long-Term Endurable 1T-DRAM Through the Use of the Biristor Mode Operation | - |
dc.type | Article | - |
dc.identifier.wosid | 000331377500024 | - |
dc.identifier.scopusid | 2-s2.0-84893846640 | - |
dc.type.rims | ART | - |
dc.citation.volume | 35 | - |
dc.citation.issue | 2 | - |
dc.citation.beginningpage | 220 | - |
dc.citation.endingpage | 222 | - |
dc.citation.publicationname | IEEE ELECTRON DEVICE LETTERS | - |
dc.identifier.doi | 10.1109/LED.2013.2295240 | - |
dc.embargo.liftdate | 9999-12-31 | - |
dc.embargo.terms | 9999-12-31 | - |
dc.contributor.localauthor | Choi, Yang-Kyu | - |
dc.contributor.nonIdAuthor | Kim, Dong-Oh | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | Bistable resistor | - |
dc.subject.keywordAuthor | biristor | - |
dc.subject.keywordAuthor | capacitorless one-transistor DRAM | - |
dc.subject.keywordAuthor | disturbance | - |
dc.subject.keywordAuthor | endurance | - |
dc.subject.keywordAuthor | 1T-DRAM mode | - |
dc.subject.keywordAuthor | biristor mode | - |
dc.subject.keywordPlus | DEVICE | - |
dc.subject.keywordPlus | RAM | - |
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