A 9 bit, 1.12 ps Resolution 2.5 b/ Stage Pipelined Time-to-Digital Converter in 65 nm CMOS Using Time-Register

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dc.contributor.authorKim, KwangSeokko
dc.contributor.authorYu, Wonsikko
dc.contributor.authorCho, SeongHwanko
dc.date.accessioned2014-08-29T02:03:24Z-
dc.date.available2014-08-29T02:03:24Z-
dc.date.created2014-05-13-
dc.date.created2014-05-13-
dc.date.created2014-05-13-
dc.date.created2014-05-13-
dc.date.issued2014-04-
dc.identifier.citationIEEE JOURNAL OF SOLID-STATE CIRCUITS, v.49, no.4, pp.1007 - 1016-
dc.identifier.issn0018-9200-
dc.identifier.urihttp://hdl.handle.net/10203/188943-
dc.description.abstractIn this paper, a 2.5 b/ stage pipelined time- to- digital converter ( TDC) is presented. For pipelined operation, a novel time- register is proposed which is capable of storing, adding and subtracting time information with a clock signal. Together with a pulse- train time- amplifier, a 9- bit synchronous pipelined TDC is implemented, which consists of three 2.5 b/ stage TDCs and a 3 b delay- line TDC. A prototype chip fabricated in 65 nm CMOS process achieves 1.12 ps of time resolution at 250 MS/ s while consuming 15.4 mW. Compared to other high- resolution state- of- the- art TDCs, the proposed pipelined TDC achieves the best figure- of- merit ( FoM) without any calibration. I-
dc.languageEnglish-
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC-
dc.titleA 9 bit, 1.12 ps Resolution 2.5 b/ Stage Pipelined Time-to-Digital Converter in 65 nm CMOS Using Time-Register-
dc.typeArticle-
dc.identifier.wosid000334114600019-
dc.identifier.scopusid2-s2.0-84897533474-
dc.type.rimsART-
dc.citation.volume49-
dc.citation.issue4-
dc.citation.beginningpage1007-
dc.citation.endingpage1016-
dc.citation.publicationnameIEEE JOURNAL OF SOLID-STATE CIRCUITS-
dc.identifier.doi10.1109/JSSC.2013.2297412-
dc.embargo.liftdate9999-12-31-
dc.embargo.terms9999-12-31-
dc.contributor.localauthorCho, SeongHwan-
dc.contributor.nonIdAuthorKim, KwangSeok-
dc.description.isOpenAccessN-
dc.type.journalArticleArticle; Proceedings Paper-
dc.subject.keywordAuthorAll-digital PLL ( ADPLL)-
dc.subject.keywordAuthorpipeline architecture-
dc.subject.keywordAuthortime-adder-
dc.subject.keywordAuthortime-domain ADC-
dc.subject.keywordAuthortime-register-
dc.subject.keywordAuthortime-subtractor-
dc.subject.keywordAuthortime-to-digital converter ( TDC)-
dc.subject.keywordAuthor2.5 b/stage.-
dc.subject.keywordAuthorAll-digital PLL ( ADPLL)-
dc.subject.keywordAuthorpipeline architecture-
dc.subject.keywordAuthortime-adder-
dc.subject.keywordAuthortime-domain ADC-
dc.subject.keywordAuthortime-register-
dc.subject.keywordAuthortime-subtractor-
dc.subject.keywordAuthortime-to-digital converter ( TDC)-
dc.subject.keywordAuthor2.5 b/stage.-
dc.subject.keywordPlusFLIGHT LASER-RADAR-
dc.subject.keywordPlusDELAY-LINE-
dc.subject.keywordPlusTDC-
dc.subject.keywordPlusARCHITECTURE-
dc.subject.keywordPlusAMPLIFIER-
dc.subject.keywordPlusFLIGHT LASER-RADAR-
dc.subject.keywordPlusDELAY-LINE-
dc.subject.keywordPlusTDC-
dc.subject.keywordPlusARCHITECTURE-
dc.subject.keywordPlusAMPLIFIER-
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