DC Field | Value | Language |
---|---|---|
dc.contributor.author | Kim, KwangSeok | ko |
dc.contributor.author | Yu, Wonsik | ko |
dc.contributor.author | Cho, SeongHwan | ko |
dc.date.accessioned | 2014-08-29T02:03:24Z | - |
dc.date.available | 2014-08-29T02:03:24Z | - |
dc.date.created | 2014-05-13 | - |
dc.date.created | 2014-05-13 | - |
dc.date.created | 2014-05-13 | - |
dc.date.created | 2014-05-13 | - |
dc.date.issued | 2014-04 | - |
dc.identifier.citation | IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.49, no.4, pp.1007 - 1016 | - |
dc.identifier.issn | 0018-9200 | - |
dc.identifier.uri | http://hdl.handle.net/10203/188943 | - |
dc.description.abstract | In this paper, a 2.5 b/ stage pipelined time- to- digital converter ( TDC) is presented. For pipelined operation, a novel time- register is proposed which is capable of storing, adding and subtracting time information with a clock signal. Together with a pulse- train time- amplifier, a 9- bit synchronous pipelined TDC is implemented, which consists of three 2.5 b/ stage TDCs and a 3 b delay- line TDC. A prototype chip fabricated in 65 nm CMOS process achieves 1.12 ps of time resolution at 250 MS/ s while consuming 15.4 mW. Compared to other high- resolution state- of- the- art TDCs, the proposed pipelined TDC achieves the best figure- of- merit ( FoM) without any calibration. I | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | A 9 bit, 1.12 ps Resolution 2.5 b/ Stage Pipelined Time-to-Digital Converter in 65 nm CMOS Using Time-Register | - |
dc.type | Article | - |
dc.identifier.wosid | 000334114600019 | - |
dc.identifier.scopusid | 2-s2.0-84897533474 | - |
dc.type.rims | ART | - |
dc.citation.volume | 49 | - |
dc.citation.issue | 4 | - |
dc.citation.beginningpage | 1007 | - |
dc.citation.endingpage | 1016 | - |
dc.citation.publicationname | IEEE JOURNAL OF SOLID-STATE CIRCUITS | - |
dc.identifier.doi | 10.1109/JSSC.2013.2297412 | - |
dc.embargo.liftdate | 9999-12-31 | - |
dc.embargo.terms | 9999-12-31 | - |
dc.contributor.localauthor | Cho, SeongHwan | - |
dc.contributor.nonIdAuthor | Kim, KwangSeok | - |
dc.description.isOpenAccess | N | - |
dc.type.journalArticle | Article; Proceedings Paper | - |
dc.subject.keywordAuthor | All-digital PLL ( ADPLL) | - |
dc.subject.keywordAuthor | pipeline architecture | - |
dc.subject.keywordAuthor | time-adder | - |
dc.subject.keywordAuthor | time-domain ADC | - |
dc.subject.keywordAuthor | time-register | - |
dc.subject.keywordAuthor | time-subtractor | - |
dc.subject.keywordAuthor | time-to-digital converter ( TDC) | - |
dc.subject.keywordAuthor | 2.5 b/stage. | - |
dc.subject.keywordAuthor | All-digital PLL ( ADPLL) | - |
dc.subject.keywordAuthor | pipeline architecture | - |
dc.subject.keywordAuthor | time-adder | - |
dc.subject.keywordAuthor | time-domain ADC | - |
dc.subject.keywordAuthor | time-register | - |
dc.subject.keywordAuthor | time-subtractor | - |
dc.subject.keywordAuthor | time-to-digital converter ( TDC) | - |
dc.subject.keywordAuthor | 2.5 b/stage. | - |
dc.subject.keywordPlus | FLIGHT LASER-RADAR | - |
dc.subject.keywordPlus | DELAY-LINE | - |
dc.subject.keywordPlus | TDC | - |
dc.subject.keywordPlus | ARCHITECTURE | - |
dc.subject.keywordPlus | AMPLIFIER | - |
dc.subject.keywordPlus | FLIGHT LASER-RADAR | - |
dc.subject.keywordPlus | DELAY-LINE | - |
dc.subject.keywordPlus | TDC | - |
dc.subject.keywordPlus | ARCHITECTURE | - |
dc.subject.keywordPlus | AMPLIFIER | - |
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