Jitter suppressed on-chip clock distribution using package plane cavity resonance

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Publisher
IEEE
Issue Date
2008-05-19
Language
ENG
Citation

2008 Asia-Pacific Symposium on Electromagnetic Compatibility and 19th International Zurich Symposium on Electromagnetic Compatibility, APEMC 2008, pp.427 - 430

URI
http://hdl.handle.net/10203/18681
Appears in Collection
EE-Conference Papers(학술회의논문)
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