RF interconnect for multi-Gbit/s board-level clock distribution

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dc.contributor.authorRyu, Woonghwanko
dc.contributor.authorLee, Junwooko
dc.contributor.authorKim, Hyungsooko
dc.contributor.authorAhn, Seungyoungko
dc.contributor.authorKim, Namhoonko
dc.contributor.authorChoi, Baekkyuko
dc.contributor.authorKam, Donggunko
dc.contributor.authorKim, Jounghoko
dc.date.accessioned2010-05-19T06:20:25Z-
dc.date.available2010-05-19T06:20:25Z-
dc.date.created2012-02-06-
dc.date.created2012-02-06-
dc.date.issued2000-08-
dc.identifier.citationIEEE TRANSACTIONS ON ADVANCED PACKAGING, v.23, no.3, pp.398 - 407-
dc.identifier.issn1521-3323-
dc.identifier.urihttp://hdl.handle.net/10203/18479-
dc.description.abstractWith clock distribution of over 1 GHz, problems associated with clock skew, power consumption, and timing jitter are becoming critical for determining the processing speed of high-performance digital systems, especially for multi-processor systems. Conventional digital clock distribution interconnection has a severe power consumption problem for GHz clock distribution because of the transmission line losses, as well as exhibiting difficult signal integrity problems due to clock skew, clock jitter and signal reflection. To overcome conventional digital clock distribution limitations, optical clock distribution techniques, based on guided-wave optics and free-space optics, have been proposed, However, the optical clock distribution is found to be bulky, hard to fabricate, and expensive, even though it has lower power consumption and excellent signal integrity properties. In this paper, a multi-Gbit/s clock distribution scheme to minimize power consumption, skew, and jitter, based on RF interconnect technology, especially for the medium clock frequency region from 200 MHz to 10 GHz, and interconnection Line lengths of from 10 cm to 3 m, is proposed. A quantitative comparison is made between the guided optical, the free-space optical, the conventional digital, and the proposed RF interconnections for board-level clock distribution relative to power consumption and speed. The proposed board-level clock distribution with 32-fan-outs has successfully demonstrated less than 22-ps skew and less than 3-ps jitter at 2 GHz. The estimated power consumption of the clock link for the proposed clock distribution has been shown to be about 320 mW Furthermore, the proposed clock receiver using the RF clock distribution scheme has demonstrated less than 2-ps dead time and 3-ps skew time.-
dc.description.sponsorshipIEEE Components, Packaging, and Manufacturing Technology Societyen
dc.languageEnglish-
dc.language.isoen_USen
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC-
dc.subjectCMOS TAPERED BUFFER-
dc.subjectSYSTEMS-
dc.subjectPOWER-
dc.subjectDESIGN-
dc.subjectSPEED-
dc.titleRF interconnect for multi-Gbit/s board-level clock distribution-
dc.typeArticle-
dc.identifier.wosid000088874600009-
dc.identifier.scopusid2-s2.0-0034238708-
dc.type.rimsART-
dc.citation.volume23-
dc.citation.issue3-
dc.citation.beginningpage398-
dc.citation.endingpage407-
dc.citation.publicationnameIEEE TRANSACTIONS ON ADVANCED PACKAGING-
dc.embargo.liftdate9999-12-31-
dc.embargo.terms9999-12-31-
dc.contributor.localauthorAhn, Seungyoung-
dc.contributor.localauthorKim, Joungho-
dc.contributor.nonIdAuthorRyu, Woonghwan-
dc.contributor.nonIdAuthorLee, Junwoo-
dc.contributor.nonIdAuthorKim, Hyungsoo-
dc.contributor.nonIdAuthorKim, Namhoon-
dc.contributor.nonIdAuthorChoi, Baekkyu-
dc.contributor.nonIdAuthorKam, Donggun-
dc.type.journalArticleArticle; Proceedings Paper-
dc.subject.keywordAuthorboard-level clock distribution-
dc.subject.keywordAuthorhigh-speed digital-
dc.subject.keywordAuthorlow skew-
dc.subject.keywordAuthormultiprocessor-
dc.subject.keywordAuthorRF interconnection-
dc.subject.keywordAuthorsynchronization-
dc.subject.keywordPlusCMOS TAPERED BUFFER-
dc.subject.keywordPlusSYSTEMS-
dc.subject.keywordPlusPOWER-
dc.subject.keywordPlusDESIGN-
dc.subject.keywordPlusSPEED-
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