Contactless wafer-level TSV connectivity testing and embedded current measurement using magnetic coupling = 자계 결합을 이용한 비접촉식 관통 실리콘 비아 연결성 테스트 및 전류 신호 측정

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Nowadays, in order to achieve higher density of integrated circuit increases, the design layout of IC is changing quickly from two-dimensional to three-dimensional. The major current focus in three-dimensional integrated circuit (3D IC) is how to connect chips vertically. Among vertical interconnection technologies such as bond wire, flip chip, and through silicon via (TSV), TSV has proven to be a remarkable technological leap to achieve a high level in not only the degree of integration but also in electrical performance. However, as the number of TSVs is expected to increase dramatically with the demand of high band-width while maintaining low power consumption, testing issues have come to gain much attention. TSV, while it can provide a remarkable leap forward in achieving much denser chip design, fabrication processes still exhibit instability and unreliability as the technology is quite new, and a lot of issues have not been handled and analyzed yet. As was depicted in recently reported data, with increasing number of TSVs, the final yield of the chip is expected to decrease drastically. And since TSVs are expected to be of much importance for the electrical performance of the system in the future, it is essential to test whether TSVs are electrically fully connected without any failure, such as disconnections. Moreover, as 3D-IC enables the integration of heterogeneous technologies for each sub-system with much less area consumption, many advantages in terms of area consumption and data bandwidth can be brought along. However, since many different logics are integrated very close to one another, a new serious noise coupling issues are raised by the 3D stacking of ICs; namely, vertical noise coupling between stacked-ICs in a mixed signal stacked 3D-IC. Because of the small separatation of only a few tens of μm between each thinned stacked-IC, a signal can be coupled into other ICs via tight near-field coupling, and guaranteeing the performance of each l...
Advisors
Kim, Joung-Horesearcher김정호
Description
한국과학기술원 : 전기및전자공학과,
Publisher
한국과학기술원
Issue Date
2013
Identifier
513262/325007  / 020113154
Language
eng
Description

학위논문(석사) - 한국과학기술원 : 전기및전자공학과, 2013.2, [ vi, 46 p. ]

Keywords

Through-Silicon Via (TSV); Contactless testing; Current Measurement; Magnetic Coupling; 관통 실리콘 비아; 비접촉식 테스트; 전류 신호 측정; 자계 결합; 관통 실리콘 비아 연결성 테스트; TSV connectivity testing

URI
http://hdl.handle.net/10203/181043
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=513262&flag=dissertation
Appears in Collection
EE-Theses_Master(석사논문)
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