Static energy minimization of 3D-stacked L2 cache with selective cache compression

Abstract

Three-dimentional (3D) integration is one of the most promising approaches to increase cache bandwidth and to reduce the wire length and thereby, the delay and transmission power consumption. But, high power density in 3D IC due to high integration incurs significant leakage current increment which leads to high static energy consumption. In deep sub-micron technologies, leakage current problem in 3D-stacked large L2 cache is more serious than in conventional 2D ICs. In this paper, to mitigate the static energy consumption of L2 cache in 3D IC, we firstly propose a selective cache compression approach coupled with SRAM power-gating technique for L2 cache in 3D IC. We select cache lines to be compressed according to the access characteristics in a dynamic manner, which reduces the decompression overheads and thereby reduces the overall energy consumption. We also employ a special temporal buffer between decompression engine and L1 cache to further reduce the energy consumption. The experimental results show that our approach achieves up to 40% (average 22%) energy reduction with negligible performance overhead compared with the conventional cache management policy.