A stochastic reference clock generator (SRCG) working with encoded data is presented in this paper. As SRCG has only single D-flipflop operating line-rate and all the other component operating in divided rate, it is suitable for low power clock and data recovery system (CDR). SRCG extracts frequency information directly from incoming data and creates clock-like signal. However, the average frequency of SRCG is not only related to data rate, also transition density of data. The encoded data with unexpected transition density causes the frequency offset of voltage controlled oscillator (VCO). The proposed scheme has adaptive frequency divider which can select the optimum division ratio of SRCG. Therefore, the average frequency of SRCG is always con-stant value regardless of the transition density of incoming data. The proposed adaptive frequency divider is fabricated by 90nm CMOS process and 0.55mW power consumption at 2.7Gbps data.