Data format insensitive SRCG using an adaptive frequency divider = 적응 주파수 분주기를 이용한 데이터 포맷 둔감형 통계적 기준 발진기

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A stochastic reference clock generator (SRCG) working with encoded data is presented in this paper. As SRCG has only single D-flipflop operating line-rate and all the other component operating in divided rate, it is suitable for low power clock and data recovery system (CDR). SRCG extracts frequency information directly from incoming data and creates clock-like signal. However, the average frequency of SRCG is not only related to data rate, also transition density of data. The encoded data with unexpected transition density causes the frequency offset of voltage controlled oscillator (VCO). The proposed scheme has adaptive frequency divider which can select the optimum division ratio of SRCG. Therefore, the average frequency of SRCG is always con-stant value regardless of the transition density of incoming data. The proposed adaptive frequency divider is fabricated by 90nm CMOS process and 0.55mW power consumption at 2.7Gbps data.
Advisors
Bae, Hyeon-Minresearcher배현민
Description
한국과학기술원 : 전기및전자공학과,
Publisher
한국과학기술원
Issue Date
2013
Identifier
513294/325007  / 020113345
Language
eng
Description

학위논문(석사) - 한국과학기술원 : 전기및전자공학과, 2013.2, [ iv, 36 p. ]

Keywords

clock and data recovery; SRCG; transition density; data format; 클럭-데이터 복원; 기준발진기; 천이밀도; 지터감소; jitter reduction

URI
http://hdl.handle.net/10203/181016
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=513294&flag=dissertation
Appears in Collection
EE-Theses_Master(석사논문)
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