DC Field | Value | Language |
---|---|---|
dc.contributor.advisor | Cho, Seong-Hwan | - |
dc.contributor.advisor | 조성환 | - |
dc.contributor.author | Jo, Young-Woo | - |
dc.contributor.author | 조영우 | - |
dc.date.accessioned | 2013-09-12T02:01:15Z | - |
dc.date.available | 2013-09-12T02:01:15Z | - |
dc.date.issued | 2013 | - |
dc.identifier.uri | http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=513370&flag=dissertation | - |
dc.identifier.uri | http://hdl.handle.net/10203/180978 | - |
dc.description | 학위논문(석사) - 한국과학기술원 : 전기및전자공학과, 2013.2, [ iii, 26 p. ] | - |
dc.description.abstract | The lab-on-a-chip technology covers the design and development of bio-tools for drug discovery, diagnostics, and tissue engineering. This technology targets to integrate these devices on a minimum scale with low cost. We are here concerned with the manipulating cell for medical applications such as cell culture, cell therapy and diagnostics. For these purposes, a variety of cell manipulation methods are proposed and developed over the past decade. But, this technique requires a bulk and expensive equipment. The work here is of a dielectrophoresis(DEP) based single cell trapping on-chip system aiming at analyzing the cell’s electrical properties. For suspended particles in water, the dielectric constant is less than the dielectric constant of water. Consequently, the particles are repelled from regions of high electric field intensities. This phenomenon is called negative DEP. The proposed architecture concentrates to generate DEP force on single chip. The system using CMOS technologies for DEP systems can take several advantages of CMOS technologies in terms of size and cost. To create an electric field, the system consists of signal generator and patterned electrode arrays. The electrode arrays are patterned with particular shapes into glass substrate and CMOS IC to generate the negative DEP force. To create higher electric field, the opening layer of the CMOS process is used. The finite element software COMSOL Multiphysics has been used to perform the numerical simulation. The proposed system has been tested with red blood cells. Generating negative DEP force on glass substrate is successfully verified and electric field on the CMOS IC is also verified. | eng |
dc.language | eng | - |
dc.publisher | 한국과학기술원 | - |
dc.subject | cell trapping | - |
dc.subject | on-chip | - |
dc.subject | 세포 포획 | - |
dc.subject | 유전영동 | - |
dc.subject | dielectrophoresis | - |
dc.title | Analysis and design of on-chip single cell trapping system using dielectrophoresis | - |
dc.title.alternative | 유전영동을 이용한 단일 세포 포획하는 IC 시스템의 설계 및 분석 | - |
dc.type | Thesis(Master) | - |
dc.identifier.CNRN | 513370/325007 | - |
dc.description.department | 한국과학기술원 : 전기및전자공학과, | - |
dc.identifier.uid | 020113604 | - |
dc.contributor.localauthor | Cho, Seong-Hwan | - |
dc.contributor.localauthor | 조성환 | - |
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