Eye-diagram estimation method for high-speed interconnect in through-silicon via (TSV) based three-dimensional IC (3-D IC) = 실리콘 관통 비아 기반 3차원 IC의 고속 채널을 위한 아이-다이어그램 예측 방법

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In Through-silicon via (TSV) based three-dimensional integrated circuit (3-D IC), three-dimensional interconnections are expected to realize considerable high bandwidth throughput in vertically stacked and laterally distributed ICs. However, although TSVs and a silicon interposer in TSV-based 3-D IC lead to a significant decrease of interconnect length, the received digital signal is still degraded at high data rate due to non-idealities of 3-D IC channel. Therefore, analysis of signal integrity in 3-D IC is necessary. The eye-diagram, which is a convenient and graphical method to analyze received digital signal, is usually used for analyzing the signal integrity. However, the simulation and measurement of the eye-diagram have several limitations, such as time consuming and fabrications of 3-D IC test vehicles. Moreover, though there has been the previous works for estimating the eye-diagram, these methods have the limitations of accuracy and the estimation time. In this thesis, the precise and fast eye-diagram estimation method is proposed, verified and applied to the optimization of the 3-D IC channels. As mentioned before, the previous eye-diagram estimation methods have several limitations, because they use the simplified channel model or time-consuming processes. There-fore, the proposed method uses the equivalent-circuit model of 3-D IC channel and the equation-based calculation, and they compensate the accuracy and the estimation time, respectively. For verifying the accuracy and the fast estimation time, the comparison result between the proposed method and the full-wave simulation are presented. The result shows that the estimated eye-diagram using the proposed method is almost same with the eye-diagram using the full-wave simulation, and the estimation time is much faster. Moreover, the verification result of the proposed method by measuring the fabricated test vehicles, which contain TSV and the silicon interposer interconnect, are also presented....
Advisors
Kim, Joung-Horesearcher김정호researcher
Description
한국과학기술원 : 전기 및 전자공학과,
Publisher
한국과학기술원
Issue Date
2011
Identifier
467882/325007  / 020093154
Language
eng
Description

학위논문(석사) - 한국과학기술원 : 전기 및 전자공학과, 2011.2, [ vii, 61 p. ]

Keywords

Three-dimensional IC; Through-silicon via; Silicon interposer; 3차원 IC; 실리콘 관통 비아; 실리콘 인터포져; 아이-다이어그램 예측; Eye-diagram estimation

URI
http://hdl.handle.net/10203/180739
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=467882&flag=dissertation
Appears in Collection
EE-Theses_Master(석사논문)
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