Source-based memory scheduling for manycore accelerators = 다중코어 가속기 아키텍쳐에서의 코어기반 메모리 스케쥴링

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dc.contributor.advisorKim, John Dong-Jun-
dc.contributor.advisor김동준-
dc.contributor.authorKim, Yong-Gon-
dc.contributor.author김용곤-
dc.date.accessioned2013-09-12T01:52:00Z-
dc.date.available2013-09-12T01:52:00Z-
dc.date.issued2011-
dc.identifier.urihttp://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=467948&flag=dissertation-
dc.identifier.urihttp://hdl.handle.net/10203/180590-
dc.description학위논문(석사) - 한국과학기술원 : 전산학과, 2011.2, [ v, 27 p. ]-
dc.description.abstractThe increasing number of cores in graphics processing units (GPU) and memory bandwidth requirements of these cores have placed more demand on the memory bandwidth. Memory controllers in these systems often employ out-of-order scheduling to maximize row access locality. However, this requires complex logic to enable out-of-order scheduling. To provide a low-cost and low-complexity memory scheduling, we propose source-based memory scheduling where memory access is scheduled at the injection of the shader cores. We propose two complementary techniques-dram-aware source throttling and superpackets. For highly parallel, non-graphics applications, memory access requests from shader cores have been shown to result in significant row locality but the locality is destroyed in the on-chip network. We show how the requests can be group together into a single superpacket prior to injection to maintain the row locality without increasing the complexity of any component such as the memory scheduler or the on-chip network. We use local, distributed throttling mechanism to achieve dram-aware memory scheduling and reduce the network congestion caused by full of memory controller queue. By combing these techniques of superpacket and dram-aware scheduling, the performance across a wide range of application is within 93% of the complex FR-FCFS on average while exceeding the performance of previously proposed on-chip network modification by 13% and at significantly lower cost and complexity.eng
dc.languageeng-
dc.publisher한국과학기술원-
dc.subjectComputer-
dc.subjectArchitecture-
dc.subjectManycore Accelerator-
dc.subject컴퓨터-
dc.subject아키텍쳐-
dc.subject가속기 아키텍쳐-
dc.subject메모리스케쥴링-
dc.subjectMemory Scheduling-
dc.titleSource-based memory scheduling for manycore accelerators = 다중코어 가속기 아키텍쳐에서의 코어기반 메모리 스케쥴링-
dc.typeThesis(Master)-
dc.identifier.CNRN467948/325007 -
dc.description.department한국과학기술원 : 전산학과, -
dc.identifier.uid020083112-
dc.contributor.localauthorKim, John Dong-Jun-
dc.contributor.localauthor김동준-
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EE-Theses_Master(석사논문)
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