Prefetch-aware on-chip networks for multi-core architecture프리페치를 고려한 온 칩 네트워크 디자인

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In chip multiprocessors (CMPs), on-chip networks are shared resources among many components on a chip and are sensitive to the volume of network traffics generated from such components. Meanwhile, although prefectching techniques can help improve system performance in general, these techniques have a disadvantage of generating a large amount of additional on-chip network traffics which could waste network bandwidth. Because of the characteristics, on-chip networks and prefetching techniques can conflict with each other, and hence this conflict can slow down system performance in CMPs. For example, on ideal on-chip networks, which have unlimited bandwidth, prefetching techniques can improve system performance as expected. However, in contrast, in real on-chip networks considering congestion, such prefetching techniques are not able to function optimally because on-chip networks would be congested by additional prefetching packets. Like this example, if the effect of on-chip networks is not properly considered, prefetching techniques can not improve overall system performance in CMPs. Therefore, we need to make on-chip networks consider prefetching traffics in order to improve system performance in CMPs using on-chip networks. In this paper, we propose two techniques related to on-chip network designs for overcoming congestion caused by additional network traffics of prefetching techniques. First, we propose Router Arbitration for Prefetch (RAP) as a new arbitration mechanism at routers on on-chip networks. The RAP gives a chance to demand requests more than prefetch requests at time of an arbitration of packets. Second, we propose Request Throttling for Prefetch (RTP) as a throttling mechanism of prefetch packets at a source of prefetching techniques when the congestion in on-chip networks happens. Both approaches try to maximize performance of prefethcing techniques even when the congestion in on-chip networks is severe. According to our evaluation, the RAP...
Advisors
Huh, Jae-Hyukresearcher허재혁researcher
Description
한국과학기술원 : 전산학과,
Publisher
한국과학기술원
Issue Date
2011
Identifier
467934/325007  / 020093405
Language
eng
Description

학위논문(석사) - 한국과학기술원 : 전산학과, 2011.2, [ iv, 39 p. ]

Keywords

CMPs; On-chip networks; Prefetch; Congestion control; 칩멀티프로세서; 온칩네트워크; 프리페치; 혼잡제어; 메세지 조절; Message throttling

URI
http://hdl.handle.net/10203/180570
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=467934&flag=dissertation
Appears in Collection
CS-Theses_Master(석사논문)
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