Pulsed-Latch-Based ASIC design for high performance and low power = 펄스래치기반 고성능 저전력 ASIC 설계

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Advisors
Shin, Young-Sooresearcher신영수
Description
한국과학기술원 : 전기 및 전자공학과,
Publisher
한국과학기술원
Issue Date
2011
Identifier
482643/325007  / 020087113
Language
eng
Description

학위논문(박사) - 한국과학기술원 : 전기 및 전자공학과, 2011.8, [ xi, 132 p. ]

Keywords

pulsed-latch; low power; 펄스래치; 저전력; 성능최적화; timing optimization

URI
http://hdl.handle.net/10203/180227
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=482643&flag=dissertation
Appears in Collection
EE-Theses_Ph.D.(박사논문)
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