DC Field | Value | Language |
---|---|---|
dc.contributor.advisor | Cho, Seong-Hwan | - |
dc.contributor.advisor | 조성환 | - |
dc.contributor.author | Park, Pyoung-Won | - |
dc.contributor.author | 박평원 | - |
dc.date.accessioned | 2013-09-11T05:14:54Z | - |
dc.date.available | 2013-09-11T05:14:54Z | - |
dc.date.issued | 2012 | - |
dc.identifier.uri | http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=486681&flag=dissertation | - |
dc.identifier.uri | http://hdl.handle.net/10203/180195 | - |
dc.description | 학위논문(박사) - 한국과학기술원 : 전기 및 전자공학과, 2012.2, [ vi, 71 p. ] | - |
dc.description.abstract | In this thesis, two techniques for low-noise and low-jitter PLLs are proposed. One is for a delta-sigma fractional-N frequency synthesizer and the other is for a finite-modulo clock generator. The difference between two cases is the former exploits the delta-sigma modulator(DSM) to increase the frequency resolution and the latter doesn`t. In each case, different approaches are introduced to achieve low-noise or low-jitter performance. In the early chapters of the thesis, a low-noise, wide-bandwidth fractional-N frequency synthesizer based on a nested-PLL architecture is introduced. In order to reduce the quantization noise of the DSM, it is clocked at nine times the reference frequency so that the quantization noise is spread to higher frequencies. By doing this, it is easier to filter out the quantization noise using same PLL loop bandwidth. Increasing the operating frequency of the DSM is done by splitting the feedback divider into two sub-dividers where Divider1 with division ratio N1 and Divider2 with the division ratio N2. The DSM is clocked by the output of the Divider1 whose output is nine times the reference frequency when PLL is locked. Unfortunately, to increase the operating frequency of the DSM causes noise aliasing since a Divider2 performs moving average and down sampling. In order to solve the noise aliasing, an anti-aliasing filter that operates in the phase domain is added between two sub-dividers. In this work, we exploit the fact that PLL is a good low-pass filter operating in the phase domain. Prototypes have been implemented in 0.13¼m CMOS using ring and LC VCO, where the ring version achieves 26.3dB quantization noise suppression while consuming 15.2mW and LC version consumes 9.6mW. In the latter half of the thesis, a finite-modulo clock generator is proposed that uses a fractional injection locking technique. Although the conventional injection locking technique reduces the jitter of the oscillator, it cannot operates with the oscillator whose... | eng |
dc.language | eng | - |
dc.publisher | 한국과학기술원 | - |
dc.subject | Phase-locked Loop | - |
dc.subject | Low-Noise | - |
dc.subject | Low-Jitter | - |
dc.subject | Clock generator | - |
dc.subject | 위상고정루프 | - |
dc.subject | 저잡음 | - |
dc.subject | 주파수합성기 | - |
dc.subject | 클럭발생기 | - |
dc.subject | Frequency Synthesizer | - |
dc.title | Techniques of low-noise PLLs for frequency synthesis and clock generation | - |
dc.title.alternative | 주파수 합성기와 클럭 발생기를 위한 저잡음 위상고정루프 설계 | - |
dc.type | Thesis(Ph.D) | - |
dc.identifier.CNRN | 486681/325007 | - |
dc.description.department | 한국과학기술원 : 전기 및 전자공학과, | - |
dc.identifier.uid | 020085268 | - |
dc.contributor.localauthor | Cho, Seong-Hwan | - |
dc.contributor.localauthor | 조성환 | - |
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