Measurement and analysis of the package-level eye diagram using on-chip signal integrity analyzer (OSIA) in high speed serial link고속 직렬 링크에서의 신호 무결성 분석기를 이용한 패키지 레벨의 Eye Diagram의 측정과 분석

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In these days, high speed communication is more and more important issue for digital system design. In the near future, data transmission speed will be increasing up to several Gbps such as commercial standard SONET, SATA, USB 3.0 and so on. For successful high speed data transmission, bandwidth limitation of designed I/O channel becomes more critical factor than on-chip clock speed. In general development stage, off-chip channel measurement is one of the conventional and effective verification methods about high speed data channel. However, off-chip channel measurement has disadvantage and limitation for completed channel verification. Therefore, enhanced circuit for on-chip signal measurement is suggested for alternative solution of off-chip signal measurement in this paper. In this paper, we introduce a new on-chip signal integrity analyzer (OSIA) circuit for the measurement and analysis of package-level eye diagrams in high-speed serial links. High resolution (5 mV and 5 ps) of the proposed OSIA circuit provides the most accurate package-level eye diagram up to a 12.5 Gbps data rate. The developed test chip adopts the improved data acquisition method to remove the additional replica transmitter and the additional data sampler circuit to reduce the design complexity. This scheme also makes it possible to achieve low power consumption (111 mW) and a small area overhead (235 um x 310 um) for each differential I/O pin using a 0.18-um CMOS process. Furthermore, we monitored and investigated the eye diagram distortion effects due to package-level crosstalk, simultaneous switching noise (SSN) coupling to signal line, an embedded passive equalizer, and SSN coupling on the proposed OSIA circuit from external noise source. Another issue is to develop the new passive equalizer for compensating the frequency dependent loss and to verify the performance of that equalizer using OSIA circuit. Therefore, a wideband continuous-time passive equalizer using embedded cavity...
Advisors
Kim, Joung-Horesearcher김정호
Description
한국과학기술원 : 전기및전자공학과,
Publisher
한국과학기술원
Issue Date
2012
Identifier
511894/325007  / 020075293
Language
eng
Description

학위논문(박사) - 한국과학기술원 : 전기및전자공학과, 2012.8, [ viii, 91 p. ]

Keywords

eye diagram; signal integrity; equalizer; channel model; 신호무결성; 전원무결성; 이퀄라이저; 아이다이어그램; 채널모델링; ISI

URI
http://hdl.handle.net/10203/180164
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=511894&flag=dissertation
Appears in Collection
EE-Theses_Ph.D.(박사논문)
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