Chip-to-chip vertical noise coupling from on-chip switching DC-DC converter to low noise amplifier in mixed-signal stacked 3D-IC혼성 모드 3차원 반도체 내의 온 칩 스위칭 모드 파워 서플라이에서 저잡음 증폭기로의 버티컬 노이즈 커플링

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Recently, the mobile devices are forced to integrate more and more functions, achieve high performance as much as a personal computer. At the same time, physical space to integrate them is getting smaller to meet the consumer demands for mobile devices. These extreme conditions are no longer achievable through 2D-SoC (system-on-chip), since the conventional CMOS downscaling has nearly reached its physical limits. As a substitute, stacked 3D-IC is a promising new technological solution. Denser integration can be achieved by the 3D stacking of ICs at a far lower cost and in less space. In spite of the advantage of stacked 3D-IC, serious new noise coupling issues are raised by the 3D stacking of ICs; namely, chip-to-chip vertical noise coupling between stacked-ICs in a mixed-signal stacked 3D-IC. The chip-to-chip vertical noise coupling issue is a new and severe enough to degrade the whole system performance, particularly, RF/analog circuits. Therefore, a prediction of the chip-to-chip vertical noise coupling in a design stage is very important for one-time success of the system design. Previous works on the prediction have had a trade-off between the accuracy and the simulation time. However, the trade-off is no longer acceptable since the required accuracy and model bandwidth are getting higher and the optimization process through the prediction in the design stage is still often iterative. In this dissertation, we propose a modeling method for fast and accurate prediction of the vertical noise coupling from an on-chip switching mode power supply to a low noise amplifier (LNA) in a stacked 3D-IC. The proposed modeling includes a compact and broadband multi-section lumped circuit model of the vertical noise coupling between on-chip inductor of an on-chip switching DC-DC converter and LNA and a model of noise transfer in LNA circuit. To achieve accuracy, the modeling includes consideration of high frequency effect such as a current redistribution and a phase diff...
Advisors
Kim, Joung-Horesearcher김정호
Description
한국과학기술원 : 전기및전자공학과,
Publisher
한국과학기술원
Issue Date
2012
Identifier
511902/325007  / 020085009
Language
eng
Description

학위논문(박사) - 한국과학기술원 : 전기및전자공학과, 2012.8, [ x, 72 p. ]

Keywords

chip-to-chip; vertical noise coupling; stacked 3D-IC; low noise amplifier; symbol error rate; receiver sensitivity degradation; graphene shielding; 버티컬 노이즈 커플링; on-chip switching DC-DC converter

URI
http://hdl.handle.net/10203/180161
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=511902&flag=dissertation
Appears in Collection
EE-Theses_Ph.D.(박사논문)
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