Jitter correlation maximization between data and clock in source synchronous parallel link = 소스 동기화 병렬 링크에서 데이터와 클럭간의 지터 연관성 극대화

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Markets continuously require higher speed communication, lower power consumption, and smaller size as time goes on. Now a day, due to importance of mobile devices, many people increasingly focus on energy saving. In conclusion, many recent technologies such as GDDR5, DDR3, QuickPath Interconnect (QPI), and HyperTransport adopt a source synchronous parallel link. Source synchronous parallel link (SSPL), which is also called as a forwarded-clock architecture, is an architecture that transmits clocks through channels with data. Comparing to an embedded-clock architecture (ECA) which transmits only data through channels, SSPL can achieve low power and a high speed due to high jitter correlation between data and clock. However, in SSPL, latency mismatch between data and clock reduce the jitter correlation especially at high frequency jitter. Many researches have been investigated to increase the jitter correlation in SSPL. Recently, many papers have focused on an injection-locked oscillator (ILO) because it can increase jitter correlation by filtering high frequency jitter with small overhead. However, (1) ILO has intrinsic two dependency problems that limit the jitter performance: jitter tracking bandwidth (JTB) versus clock de-skew and JTB versus a required VCO tuning range for 1UI de-skew. (2) Clock jitter filters including the ILO are susceptible to power noise as the latency mismatch between data and clock increases. (3) Finally, high frequency jitter at ILO is not totally removed by ILO but replaced by phase noise of the free running oscillator. This thesis proposes two novel SSPL receivers At first, a receiver without the two dependency problems is proposed. The optimal JTB for a clock jitter filter is analyzed to maximize the jitter correlation between data and clock. The proposed receiver achieves the optimal JTB and optimal de-skew related to the dynamic timing margin and the static timing margin simultaneously. The proposed receiver can optimize dynamic ...
Advisors
Kim, Lee-Supresearcher김이섭
Description
한국과학기술원 : 전기및전자공학과,
Publisher
한국과학기술원
Issue Date
2013
Identifier
513097/325007  / 020107085
Language
eng
Description

학위논문(박사) - 한국과학기술원 : 전기및전자공학과, 2013.2, [ ix, 87 p. ]

Keywords

forwarded-clock receiver; Source synchronous parallel link; injection-locked oscillator (ILO); clock jitter filter; open-loop multiphase generator (OLMG); data jitter mixer; 소스 동기화 병렬 링크; 클럭 전송 수신기; 주입 고정 발진기; 클럭 지터 필터; jitter tracking bandwidth (JTB)

URI
http://hdl.handle.net/10203/180118
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=513097&flag=dissertation
Appears in Collection
EE-Theses_Ph.D.(박사논문)
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