This paper presents a hardware design of high throughput, low latency preamble detector for 3GPP LIE physical random access channel (PRACH) receiver. The presented PRACH receiver uses the pipelined structure to improve the throughput of power delay profile (PDP) generation which is executed multiple times during the preamble detection. In addition, to reduce detection latency, we propose an instantaneous preamble detection method for both restricted and unrestricted set. The proposed preamble detection method can detect all existing preambles directly and instantaneously from PDP output while conducting PDP combining for restricted set. The PDP combining enables the PRACH receiver to detect preambles robustly even in severe Doppler effect or frequency error exist. Using proposed method, the worst case preamble detection latency time can be less than 1 ms with 136 MHz clock and the proposed PRACH receiver can be implemented with approximately 237k equivalent ASIC gates count or occupying 30.2% of xc6v1x130t FPGA device.