Investigation of Silicon Nanowire Gate-All-Around Junctionless Transistors Built on a Bulk Substrate

Abstract

A silicon nanowire (Si-NW) with a gate-all-around (GAA) structure is implemented on a bulk wafer for a junctionless (JL) field-effect transistor (FET). A suspended Si-NW from the bulk-Si is realized using a deep reactive ion etching (RIE) process. The RIE process is iteratively applied to make multiply stacked Si-NWs, which can increase the on-state current when amplified with the number of iterations or enable integration of 3-D stacked Flash memory. The fabricated JL FETs exhibit excellent electrostatic control with the aid of the GAA and junction-free structure. The influence on device characteristics according to the channel dimensions and additional doping at the source and drain extension are studied for various geometric structures of the Si-NW.