A 145W 88 parallel multiplier based on optimized bypassing architecture
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Hong, S. | ko |
| dc.contributor.author | Roh, T. | ko |
| dc.contributor.author | Yoo, Hoi-Jun | ko |
| dc.date.accessioned | 2013-03-28T08:59:05Z | - |
| dc.date.available | 2013-03-28T08:59:05Z | - |
| dc.date.created | 2012-02-06 | - |
| dc.date.created | 2012-02-06 | - |
| dc.date.issued | 2011-05-15 | - |
| dc.identifier.citation | 2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011, pp.1175 - 1178 | - |
| dc.identifier.issn | 0271-4310 | - |
| dc.identifier.uri | http://hdl.handle.net/10203/164324 | - |
| dc.language | English | - |
| dc.publisher | IEEE | - |
| dc.title | A 145W 88 parallel multiplier based on optimized bypassing architecture | - |
| dc.type | Conference | - |
| dc.identifier.wosid | 000297265301099 | - |
| dc.identifier.scopusid | 2-s2.0-79960885852 | - |
| dc.type.rims | CONF | - |
| dc.citation.beginningpage | 1175 | - |
| dc.citation.endingpage | 1178 | - |
| dc.citation.publicationname | 2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011 | - |
| dc.identifier.conferencecountry | BL | - |
| dc.identifier.conferencelocation | Rio de Janeiro | - |
| dc.contributor.localauthor | Yoo, Hoi-Jun | - |
| dc.contributor.nonIdAuthor | Hong, S. | - |
| dc.contributor.nonIdAuthor | Roh, T. | - |
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