A designated clock generation and distribution (DCGD) chip scheme for substrate noise-free 3-D stacked SiP design
- Publisher
- APEMC 2010
- Issue Date
- 2010-04-12
- Language
- English
- Citation
2010 Asia-Pacific Symposium on Electromagnetic Compatibility, APEMC 2010, pp.334 - 337
- Appears in Collection
- EE-Conference Papers(학술회의논문)
- Files in This Item
- There are no files associated with this item.
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