Investigation of Gate Misalignment Effects in FinFETs

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dc.contributor.authorChoi, Yang-Kyu-
dc.contributor.authorKim, Kuk-Hwan-
dc.contributor.authorHan, Jin-Woo-
dc.date.accessioned2013-03-18T11:09:58Z-
dc.date.available2013-03-18T11:09:58Z-
dc.date.created2012-02-06-
dc.date.issued2006-07-
dc.identifier.citationAsia-Pacific Workshop on Fundamental and Application of Advanced Semiconductor Devices, v., no., pp.179 - 184-
dc.identifier.urihttp://hdl.handle.net/10203/147757-
dc.languageENG-
dc.titleInvestigation of Gate Misalignment Effects in FinFETs-
dc.typeConference-
dc.type.rimsCONF-
dc.citation.beginningpage179-
dc.citation.endingpage184-
dc.citation.publicationnameAsia-Pacific Workshop on Fundamental and Application of Advanced Semiconductor Devices-
dc.identifier.conferencecountryJapan-
dc.identifier.conferencecountryJapan-
dc.contributor.localauthorChoi, Yang-Kyu-
dc.contributor.nonIdAuthorKim, Kuk-Hwan-
dc.contributor.nonIdAuthorHan, Jin-Woo-
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EE-Conference Papers(학술회의논문)
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