DC Field | Value | Language |
---|---|---|
dc.contributor.author | 탁연지 | - |
dc.contributor.author | 정윤호 | - |
dc.contributor.author | 김재석 | - |
dc.contributor.author | 박현철 | - |
dc.contributor.author | 김동규 | - |
dc.contributor.author | 박준현 | - |
dc.contributor.author | 유봉위 | - |
dc.date.accessioned | 2013-03-16T16:02:17Z | - |
dc.date.available | 2013-03-16T16:02:17Z | - |
dc.date.created | 2012-02-06 | - |
dc.date.issued | 2000-11-25 | - |
dc.identifier.citation | 대한전자공학회 2000년 추계종합학술발표회, v., no., pp.297 - 300 | - |
dc.identifier.uri | http://hdl.handle.net/10203/132937 | - |
dc.description.abstract | This paper proposes a high-speed and area-efficient FFT algorithm and performs a hardware implementation. This algorithm, named by "Radix-4/2", uses the feature of existing radix-2^3 algorithm, It reduces the number of non-trivial multipliers in SFG to the ratio of 3 to 2 compared with radix-2 or radix-4 algorithm and radix-4/2 has also twice throughput as radix-2^3 algorithm's. It is proved that FFT processor using the proposed algorithm and 64-point MDC pipeline architecture has twice throughput as radix-2^3 algorithm's, and reduces areas by 25 percentages in contrast to radix-4 algorithm's. | - |
dc.language | KOR | - |
dc.publisher | 대한전자공학회 | - |
dc.title | 고속 및 면적 효율적인 FFT 알고리즘 개발 및 하드웨어 구현 | - |
dc.title.alternative | A High Speed and Area Efficient FFT Algorithm and Its Hardware Implementation | - |
dc.type | Conference | - |
dc.type.rims | CONF | - |
dc.citation.beginningpage | 297 | - |
dc.citation.endingpage | 300 | - |
dc.citation.publicationname | 대한전자공학회 2000년 추계종합학술발표회 | - |
dc.identifier.conferencecountry | South Korea | - |
dc.contributor.localauthor | 박현철 | - |
dc.contributor.nonIdAuthor | 탁연지 | - |
dc.contributor.nonIdAuthor | 정윤호 | - |
dc.contributor.nonIdAuthor | 김재석 | - |
dc.contributor.nonIdAuthor | 김동규 | - |
dc.contributor.nonIdAuthor | 박준현 | - |
dc.contributor.nonIdAuthor | 유봉위 | - |
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