고속 및 면적 효율적인 FFT 알고리즘 개발 및 하드웨어 구현A High Speed and Area Efficient FFT Algorithm and Its Hardware Implementation

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This paper proposes a high-speed and area-efficient FFT algorithm and performs a hardware implementation. This algorithm, named by "Radix-4/2", uses the feature of existing radix-2^3 algorithm, It reduces the number of non-trivial multipliers in SFG to the ratio of 3 to 2 compared with radix-2 or radix-4 algorithm and radix-4/2 has also twice throughput as radix-2^3 algorithm's. It is proved that FFT processor using the proposed algorithm and 64-point MDC pipeline architecture has twice throughput as radix-2^3 algorithm's, and reduces areas by 25 percentages in contrast to radix-4 algorithm's.
Publisher
대한전자공학회
Issue Date
2000-11-25
Language
KOR
Citation

대한전자공학회 2000년 추계종합학술발표회, pp.297 - 300

URI
http://hdl.handle.net/10203/132937
Appears in Collection
EE-Conference Papers(학술회의논문)
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