Calulation of Trap Densities between BST/Pt Interface from Capacitance-Voltage Characteristics and Rapid Thermal Annealing Fttect for DRAM Application
- Issue Date
- 1997-02-01
- Language
- KOR
- Citation
제 4회 한국반도체 학술대회, pp.0 - 0
- Appears in Collection
- EE-Conference Papers(학술회의논문)
- Files in This Item
- There are no files associated with this item.
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