DC Field | Value | Language |
---|---|---|
dc.contributor.author | Roh, GT | ko |
dc.contributor.author | Lee, Yong-Hoon | ko |
dc.contributor.author | Kim, B | ko |
dc.date.accessioned | 2009-11-09T02:22:57Z | - |
dc.date.available | 2009-11-09T02:22:57Z | - |
dc.date.created | 2012-02-06 | - |
dc.date.created | 2012-02-06 | - |
dc.date.issued | 1997-09 | - |
dc.identifier.citation | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING, v.44, no.9, pp.729 - 740 | - |
dc.identifier.issn | 1057-7130 | - |
dc.identifier.uri | http://hdl.handle.net/10203/12238 | - |
dc.description.abstract | In this paper, we propose a new optimum phase-acquisition algorithm controlling the loop gain of a charge-pump PLL (CP-PLL) in the sense of the MMSE criterion, A set of recursive difference equations minimizing rms jitter of output phase is derived to obtain an optimum gear-shifting sequence with a zero-phase start (ZPS) assumption, It is shown that the optimum gear-shifting sequence is independent of the variance of the input phase jitter. A procedure for applying this sequence to the design of CP-PLL circuits is described. Both behavioral simulation and HSPICE circuit-level simulation demonstrate that the proposed design leads to an efficient CP-PLL having both fast acquisition and significant jitter reduction characteristics. The optimal gear-shifting CP-PLL outperforms the conventional CP-PLL's. These methods can be used for clock recovery applications such as data communication receivers, disk drive read/write channels, and local area networks, as well as for other applications requiring very short initial preamble periods. | - |
dc.language | English | - |
dc.language.iso | en_US | en |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.subject | LOCKED LOOP | - |
dc.subject | CLOCK | - |
dc.subject | CIRCUITS | - |
dc.title | Optimum phase-acquisition technique for charge-pump PLL | - |
dc.type | Article | - |
dc.identifier.wosid | A1997XU98900005 | - |
dc.identifier.scopusid | 2-s2.0-0031233489 | - |
dc.type.rims | ART | - |
dc.citation.volume | 44 | - |
dc.citation.issue | 9 | - |
dc.citation.beginningpage | 729 | - |
dc.citation.endingpage | 740 | - |
dc.citation.publicationname | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING | - |
dc.embargo.liftdate | 9999-12-31 | - |
dc.embargo.terms | 9999-12-31 | - |
dc.contributor.localauthor | Lee, Yong-Hoon | - |
dc.contributor.localauthor | Kim, B | - |
dc.contributor.nonIdAuthor | Roh, GT | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | charge-pump PLL (CP-PLL) | - |
dc.subject.keywordAuthor | gear-shifting | - |
dc.subject.keywordAuthor | MMSE criterion | - |
dc.subject.keywordAuthor | optimum sequence | - |
dc.subject.keywordAuthor | phase-acquisition | - |
dc.subject.keywordAuthor | zero-phase start (ZPS) | - |
dc.subject.keywordPlus | LOCKED LOOP | - |
dc.subject.keywordPlus | CLOCK | - |
dc.subject.keywordPlus | CIRCUITS | - |
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