DC Field | Value | Language |
---|---|---|
dc.contributor.author | Kim, JT | ko |
dc.contributor.author | Lee, Yong-Hoon | ko |
dc.contributor.author | Isshiki, T | ko |
dc.contributor.author | Kunieda, H | ko |
dc.date.accessioned | 2009-10-06T08:56:11Z | - |
dc.date.available | 2009-10-06T08:56:11Z | - |
dc.date.created | 2012-02-06 | - |
dc.date.created | 2012-02-06 | - |
dc.date.issued | 1998-08 | - |
dc.identifier.citation | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING, v.45, no.8, pp.1031 - 1043 | - |
dc.identifier.issn | 1057-7130 | - |
dc.identifier.uri | http://hdl.handle.net/10203/11671 | - |
dc.description.abstract | In this paper, we develop a scalable VLSI architecture employing a two-channel quadrature mirror filter (QMF) lattice for the one-dimensional (1-D) discrete wavelet transform (DWT). We begin with the development of systematic scheduling, which determines the filtering instants of each resolution level, on the basis of a binary tree. Then input-output relation between lattices of the QMF bank is derived, and a new structure for the data format converter (DFC) which controls the data transfer between resolution levels is proposed. In addition, implementation of a delay control unit (DCU) that controls the delay between lattices of the QMF is proposed, The structures for the DFC and DCU are regular, scalable, and require a minimum number of registers, and thereby lead to an efficient and scalable architecture for the DWT, A scalable architecture for the inverse DWT is also developed in a similar manner. Finally, pipelining of the proposed architecture is considered. | - |
dc.language | English | - |
dc.language.iso | en_US | en |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.subject | FILTER BANKS | - |
dc.title | Scalable VLSI architectures for lattice structure-based discrete wavelet transform | - |
dc.type | Article | - |
dc.identifier.wosid | 000075817000009 | - |
dc.identifier.scopusid | 2-s2.0-0032139076 | - |
dc.type.rims | ART | - |
dc.citation.volume | 45 | - |
dc.citation.issue | 8 | - |
dc.citation.beginningpage | 1031 | - |
dc.citation.endingpage | 1043 | - |
dc.citation.publicationname | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING | - |
dc.embargo.liftdate | 9999-12-31 | - |
dc.embargo.terms | 9999-12-31 | - |
dc.contributor.localauthor | Lee, Yong-Hoon | - |
dc.contributor.nonIdAuthor | Kim, JT | - |
dc.contributor.nonIdAuthor | Isshiki, T | - |
dc.contributor.nonIdAuthor | Kunieda, H | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | DCU | - |
dc.subject.keywordAuthor | DFC | - |
dc.subject.keywordAuthor | DWT | - |
dc.subject.keywordAuthor | QMF lattice | - |
dc.subject.keywordAuthor | scalable | - |
dc.subject.keywordAuthor | VLSI | - |
dc.subject.keywordPlus | FILTER BANKS | - |
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