A 20 Gb/s 1 : 4 DEMUX without inductors and low-power divide-by-2 circuit in 0.13 mu m CMOS technology

Cited 6 time in webofscience Cited 0 time in scopus
  • Hit : 1013
  • Download : 1482
In this paper, a 20 Gb/s 1:4 DEMUX without inductors is presented. A coupled latch with shared current source and buffer insertion scheme improves the signal bandwidth. A divide-by-2 circuit with a static frequency divider and a delay-locked loop achieves low power consumption and enhanced timing margin without the degradation of the divider sensitivity. A horizontal eye opening is 71.3%, and a vertical eye opening is 52%. The test chip fabricated in a 0.13 mu m process consumes 210 mW from 1.2 V logic supply.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2008-02
Language
English
Article Type
Article
Keywords

0.18-MU-M CMOS; LOGIC

Citation

IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.43, pp.541 - 549

ISSN
0018-9200
URI
http://hdl.handle.net/10203/11421
Appears in Collection
EE-Journal Papers(저널논문)
Files in This Item
This item is cited by other documents in WoS
⊙ Detail Information in WoSⓡ Click to see webofscience_button
⊙ Cited 6 items in WoS Click to see citing articles in records_button

qr_code

  • mendeley

    citeulike


rss_1.0 rss_2.0 atom_1.0