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Showing results 1 to 8 of 8

1
AVICA: An Access-time Variation Insensitive L1 Cache Architecture

Hong, Seokin; Kim, Soontae, 2013 Design Automation and Test in Europe Conference(DATE), pp.65 - 70, European Design and Automation Association (EDAA), 2013-03-19

2
Lizard: Energy-efficient hard fault detection, diagnosis and isolation in the ALU

Hong, Seokin; Kim, Soontae, 28th IEEE International Conference on Computer Design, ICCD 2010, pp.342 - 349, 2010-10-03

3
Macho: A Failure Model-oriented Adaptive Cache Architecture to enable Near-Threshold Voltage Scaling

Tayyeb Mahmood; Kim, Soontae; Hong, Seokin, IEEE International Symposium on High Performance Computer Architecture , pp.532 - 541, IEEE Computer Society, 2013-02-27

4
Partial Row Activation for Low-Power DRAM System

Lee, Yebin; Kim, Hyeonggyu; Hong, Seokin; Kim, Soontae, IEEE International Symposium on High Performance Computer Architecture, pp.217 - 228, IEEE Computer Society, 2017-02-06

5
Skinflint DRAM System: Minimizing DRAM Chip Writes for Low Power

Lee, Yebin; Kim, Soontae; Hong, Seokin; Lee, Jongmin, IEEE International Symposium on High Performance Computer Architecture , pp.25 - 34, IEEE Computer Society, 2013-02-23

6
TEPS: Transient error protection utilizing sub-word parallelism

Hong, Seokin; Kim, Soontae, 2009 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2009, pp.286 - 291, 2009-05-14

7
Ternary Cache: Three-valued MLC STT-RAM Caches

Hong, Seokin; Lee, Jongmin; Kim, Soontae, IEEE International Conference on Computer Design, IEEE Circuits and Systems Society, 2014-10-20

8
TLB Index-based Tagging for Cache Energy Reduction

Lee, Jongmin; Hong, Seokin; Kim, Soontae, ACM/IEEE International Symposium on Low Power Electronics and Design, pp.85 - 90, IEEE-CAS and ACM-SIGDA, 2011-08-01

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