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Showing results 1 to 8 of 8

1
A 186-Mvertices/s 161-mW Floating-Point Vertex Processor With Optimized Datapath and Vertex Caches

Yu, Chang-Hyo; Chung, Kyusik; Kim, Donghyun; Kim, Seok-Hoon; Kim, Lee-Sup, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.17, no.10, pp.1369 - 1382, 2009-10

2
A Dual-Shader 3-D Graphics Processor With Fast 4-D Vector Inner Product Units and Power-Aware Texture Cache

Yoon, Jae-Sung; Yu, Chang-Hyo; Kim, Dong-Hyun; Kim, Lee-Sup, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.19, no.4, pp.525 - 537, 2011-04

3
(A) multithread expanded VLIW vertex processor with vertex caches = 정점 캐쉬와 다중 쓰레드 확장 VLIW 구조를 가지는 정점 프로세서link

Changhyo Yu; 유창효; et al, 한국과학기술원, 2007

4
Code optimizations for a VLIW-style network processing unit

Kim J.; Paek Y.; Uh G., SOFTWARE-PRACTICE & EXPERIENCE, v.34, no.9, pp.847 - 874, 2004

5
Exploiting parallelism of 3D graphics geometry using a VLIW geometry processor = VLIW 기하 가속기를 이용한 3차원 그래픽의 기하연산 병렬성 강화link

Lee, Jun-Hee; 이준희; et al, 한국과학기술원, 2000

6
VLIW DSP를 위한 부동소수점 유닛의 설계 = A design of floating point unit for VLIW DSPlink

최윤석; Choi, Yun-Seok; et al, 한국과학기술원, 1998

7
VLIW 프로세서의 효율적인 Prefetch 구조의 설계 = The design of effective prefetch structure for VLIW processorlink

한경남; Han, Kyung-Nam; et al, 한국과학기술원, 1997

8
정적 포워딩에 의한 VLIW 프로세서의 데이타 hazard 처리 = Static forwarding : an approach to reduce data hazards in VLIW processorlink

박형준; Park, Hyoung-Joon; et al, 한국과학기술원, 1997

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