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Kim, Lee-Sup (김이섭) C-2032-2011

Department
School of Electrical Engineering(전기및전자공학부)
Website
http://mvlsi.kaist.ac.krHomePage
Research Area

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1

Sparse-Insertion Write Cache to Mitigate Write Disturbance Errors in Phase Change Memory

Jang, Jaemin; Shin, Wongyu; Choi, Jungwhan; et al, IEEE TRANSACTIONS ON COMPUTERS, v.68, no.5, pp.752 - 764, 2019-05

2

A 0.9-V 12-Gb/s Two-FIR Tap Direct DFE With Feedback-Signal Common-Mode Control

Lee, Daewoong; Lee, Dongil; Kim, Yong-Hun; et al, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.27, no.3, pp.724 - 728, 2019-03

3

A 0.9-V 12-Gb/s 2-FIR Tap Direct DFE with Feedback-Signal Common-Mode-Control

Lee, Daewoong; Lee, Dongil; Kim, Yong-Hun; et al, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.27, no.3, pp.724 - 728, 2019-03

4

A 10 Gb/s Reference-Less Baud-Rate CDR for Low Power Consumption with Direct Feedback Method

Kim, Yong-Hun; Lee, Dongil; Lee, Daewoong; et al, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.65, no.11, pp.1539 - 1543, 2018-11

5

A 0.65V, 11.2Gb/s Power Noise Tolerant Source-synchronous injection-locked Receiver with Direct DTLB DFE

Lee, Dongil; Kim, Yong-Hun; Lee, Daewoong; et al, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.65, no.11, pp.1564 - 1568, 2018-11

6

Elaborate Refresh: A Fine Granularity Retention Management for Deep Submicron DRAMs

Seol, Hoseok; Shin, Wongyu; Jang, Jaemin; et al, IEEE TRANSACTIONS ON COMPUTERS, v.67, no.10, pp.1403 - 1415, 2018-10

7

Energy-Efficient Design of Processing Element for Convolutional Neural Network

Choi, Yeongjae; Bae, Dongmyung; Sim, Jaehyeong; et al, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.64, no.11, pp.1332 - 1336, 2017-11

8

In-DRAM Data Initialization

Seol, Hoseok; Shin, Wongyu; Jang, Jaemin; et al, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.25, no.11, pp.3251 - 3254, 2017-11

9

Rank-Level Parallelism in DRAM

Shin, Wongyu; Jang, Jaemin; Choi, Jungwhan; et al, IEEE TRANSACTIONS ON COMPUTERS, v.66, no.7, pp.1274 - 1280, 2017-07

10

Refresh-Aware Write Recovery Memory Controller

Jang, Jaemin; Shin, Wongyu; Choi, Jungwhan; et al, IEEE TRANSACTIONS ON COMPUTERS, v.66, no.4, pp.688 - 701, 2017-04

11

An Input Data and Power Noise Inducing Clock Jitter Tolerant Reference-Less Digital CDR for LCD Intra-Panel Interface

Kim, Yonghun; Lee, Taeho; Jeon, Hyun-Kyu; et al, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, v.64, no.4, pp.823 - 835, 2017-04

12

A 5-Gb/s Digital Clock and Data Recovery Circuit With Reduced DCO Supply Noise Sensitivity Utilizing Coupling Network

Lee, Taeho; Kim, Yong Hun; Kim, Lee-Supresearcher, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.25, no.1, pp.380 - 384, 2017-01

13

A 5-Gb/s Digital Clock and Data Recovery Circuit With Reduced DCO Supply Noise Sensitivity Utilizing Coupling Network

Lee, Taeho; Kim, Yong Hun; Kim, Lee-Sup, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.25, no.1, pp.380 - 384, 2017-01

14

A Vision Processor With a Unified Interest-Point Detection and Matching Hardware for Accelerating a Stereo-Matching Algorithm

Park, Jun-Seok; Kim, Hyo-Eun; Kim, Hong-Yun; et al, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY, v.26, no.12, pp.2328 - 2343, 2016-12

15

DRAM-Latency Optimization Inspired by Relationship between Row-Access Time and Refresh Timing

Shin, Wongyu; Choi, Jungwhan; Jang, Jaemin; et al, IEEE TRANSACTIONS ON COMPUTERS, v.65, no.10, pp.3027 - 3040, 2016-10

16

A 21%-Jitter-Improved Self-Aligned Dividerless Injection-Locked PLL With a VCO Control Voltage Ripple-Compensated Phase Detector

Lee, Dongil; Lee, Taeho; Kim, Young-Ju; et al, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.63, no.8, pp.733 - 737, 2016-08

17

Q-DRAM: Quick-Access DRAM with Decoupled Restoring from Row-Activation

Shin, Wongyu; Choi, Jung Whan; Jang, Jaemin; et al, IEEE TRANSACTIONS ON COMPUTERS, v.65, no.7, pp.2213 - 2227, 2016-07

18

A 5-Gb/s 2.67-mW/Gb/s Digital Clock and Data Recovery With Hybrid Dithering Using a Time-Dithered Delta-Sigma Modulator

Lee, Taeho; Kim, Yonghun; Sim, Jaehyeong; et al, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.24, no.4, pp.1450 - 1459, 2016-04

19

A 10-Gb/s 0.71-pJ/bit Forwarded-Clock Receiver Tolerant to High-Frequency Jitter in 65-nm CMOS

Chung, Sang-Hye; Kim, Young Ju; Kim, Yonghun; et al, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.63, no.3, pp.264 - 268, 2016-03

20

A 21-Gbit/s 1.63-pJ/bit Adaptive CTLE and One-Tap DFE With Single Loop Spectrum Balancing Method

Kim, Yong-Hun; Kim, Young-Ju; Lee, Taeho; et al, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.24, no.2, pp.789 - 793, 2016-02

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