Scheduling Algorithms for Minimizing Tardiness of Orders at the Burn-in Workstation in a Semiconductor Manufacturing System

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In this paper, we consider a scheduling problem in a semiconductor test facility. We focus on the burn-in workstation and its corresponding loading/unloading workstation, which may be considered bottleneck workstations in the test facility. In the burn-in workstation, there are parallel identical batch-processing machines, called chambers, while there are unrelated parallel machines in the loading/unloading workstation. We present heuristic algorithms for the scheduling problem at the burn-in workstation as well as the loading/unloading workstation with the objective of minimizing total tardiness of orders. For evaluation of performance of the algorithms, a series of computational experiments are performed on a number of problem instances, and results show that the suggested heuristic algorithms outperform existing scheduling rules that are currently used in a real system.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2011-02
Language
English
Article Type
Article
Keywords

INCOMPATIBLE JOB FAMILIES; BATCH PROCESSING MACHINE; WAFER FABRICATION FACILITY; 2-MACHINE REENTRANT FLOWSHOP; TOTAL WEIGHTED TARDINESS; HYBRID FLOWSHOP; DISPATCHING RULES; BOUND ALGORITHM; COMPLETION-TIME; OPERATIONS

Citation

IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, v.24, no.1, pp.14 - 26

ISSN
0894-6507
DOI
10.1109/TSM.2010.2082470
URI
http://hdl.handle.net/10203/98725
Appears in Collection
IE-Journal Papers(저널논문)
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