Power Minimization for Dual- and Triple-Supply Digital Circuits via Integer Linear Programming

Abstract

This paper proposes an Integer Linear Programming (ILP)-based power minimization method by partitioning into regions, first, with three different V(DD)'s(PM3V), and, secondly, with two different V(DD)'s(PM2V). To reduce the solving time of triple-V(DD) case (PM3V), we also proposed a partitioned ILP method(p-PM3V). The proposed method provides 29% power saving on the average in the case of triple-V(DD) compared to the case of single V(DD). Power reduction of PM3V compared to Clustered Voltage Scaling (CVS) was about 18%. Compared to the un-partitioned ILP formulation(PM3V), the partitioned ILP method(p-PM3V) reduced the total solution time by 46% at the cost of additional power consumption within 1.3%.