Operation principles of 0.18-mu m four-transistor CMOS image pixels with a nonfully depleted pinned photodiode

Abstract

The operation principles of the four-transistor (4-TR) pixel CMOS image sensor, fabricated by 0.18-mu m technology, were investigated by pixel-level characterization utilizing a single-pixel test pattern. It was found that the pixel's dark current level is strongly influenced by the gate bias (V-Tx(on)) of the transfer (TX) transistor at a fixed supply voltage (V-DD)The largest dark current occurred at a conventional bias condition of V-TX(on) = V-DD = 2.5 V, but the dark current level was reduced by less than one-third at V-TX(on) = 2.1 V without degrading the pixel's charge transfer capabilities. Attributed to the dark current reduction, the fixed-pattern noise (FPN) of pixel was also decreased by up to 13.3 dB. These improvements can be explained by the more effective reset of pinned photodiode (PPD) at V-TX(on) = 2.1 V, especially in the pixel with VDD of 2.5 V or lower in which the full depletion of PPD becomes more and more difficult. In this bias condition, namely nonfully depletion condition, the TX transistor was proven to operate in the "deepest depletion" mode by effectively suppressing the electron injection from floating diffusion node to channel. Moreover, various driving signals to the TX transistor were applied to do more detailed physical analysis of the pixel operation. Since the dark current and FPN are main bottlenecks in most CMOS image sensors, the propose method is expected to efficiently improve the performance of 4-TR CMOS image pixels under 2.5 V or lower operational voltages.