Symbolic reachability analysis for multiple-clock system design

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This paper proposes a symbolic reachability analysis method for multiple-clock system design, which is the first approach to deal with both synchronization problems caused by metastability and rate mismatch problems caused by clock frequency mismatches in a single framework. Three methods are described to reproduce problems that occur with multiple-clock system design during reachability analysis: (1) alternate evaluation for a system with two clocks as the base-line model, (2) nondeterministic delayed evaluation to reproduce a synchronization problem, and (3) double evaluation to reproduce a clock frequency mismatch. Experimental results on ISCAS 89 benchmark show an improvement factor of average CPU time as compared to Clarke's method by 1.29, 55.41, 2.19 and 45.23 times when alternate evaluation, double evaluation, alternate evaluation with NDDE and double evaluation with NDDE is applied, respectively.
Publisher
WORLD SCIENTIFIC PUBL CO PTE LTD
Issue Date
2005-06
Language
English
Article Type
Article
Citation

JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, v.14, pp.533 - 551

ISSN
0218-1266
URI
http://hdl.handle.net/10203/91457
Appears in Collection
EE-Journal Papers(저널논문)
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