A due-date-based algorithm for lot-order assignment in a semiconductor wafer fabrication facility

Cited 19 time in webofscience Cited 21 time in scopus
  • Hit : 1166
  • Download : 1574
DC FieldValueLanguage
dc.contributor.authorKim, Yeong-Daeko
dc.contributor.authorBang, JYko
dc.contributor.authorAn, KYko
dc.contributor.authorLim, SKko
dc.date.accessioned2008-10-08T11:38:14Z-
dc.date.available2008-10-08T11:38:14Z-
dc.date.created2012-02-06-
dc.date.created2012-02-06-
dc.date.issued2008-05-
dc.identifier.citationIEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, v.21, pp.209 - 216-
dc.identifier.issn0894-6507-
dc.identifier.urihttp://hdl.handle.net/10203/7576-
dc.description.abstractThis paper focuses on a lot-order assignment problem, called the pegging problem, in a semiconductor wafer fabrication facility. Pegging is a process of assigning wafer lots to orders for wafers. We consider two types of pegging strategies: hard pegging strategy, under which the lot-order assignment is not changed once lots are assigned to orders; and soft pegging strategy, under which the lot-order assignment can be changed during the production period. For the soft pegging strategy, we develop three operational policies and three algorithms for the pegging problem of assigning lots to orders with the objective of minimizing total tardiness of the orders. To evaluate performance of the suggested policies and algorithms, we perform simulation experiments using real factory data as well as randomly generated data sets. Results of the simulation tests show that the repegging policies and the algorithms operated under the soft pegging strategy give better results than the hard pegging strategy.-
dc.languageEnglish-
dc.language.isoen_USen
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC-
dc.subjectDIFFUSION/OXIDATION PROCESSES-
dc.subjectSIMULATION-
dc.subjectPOLICIES-
dc.subjectRELEASE-
dc.subjectRULE-
dc.titleA due-date-based algorithm for lot-order assignment in a semiconductor wafer fabrication facility-
dc.typeArticle-
dc.identifier.wosid000255869600013-
dc.identifier.scopusid2-s2.0-43849105260-
dc.type.rimsART-
dc.citation.volume21-
dc.citation.beginningpage209-
dc.citation.endingpage216-
dc.citation.publicationnameIEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING-
dc.identifier.doi10.1109/TSM.2008.2000261-
dc.embargo.liftdate9999-12-31-
dc.embargo.terms9999-12-31-
dc.contributor.localauthorKim, Yeong-Dae-
dc.contributor.nonIdAuthorAn, KY-
dc.contributor.nonIdAuthorLim, SK-
dc.type.journalArticleArticle-
dc.subject.keywordAuthorlot-order assignment-
dc.subject.keywordAuthorscheduling-
dc.subject.keywordAuthorsemiconductor wafer fab-
dc.subject.keywordPlusDIFFUSION/OXIDATION PROCESSES-
dc.subject.keywordPlusSIMULATION-
dc.subject.keywordPlusPOLICIES-
dc.subject.keywordPlusRELEASE-
dc.subject.keywordPlusRULE-
Appears in Collection
IE-Journal Papers(저널논문)
Files in This Item
This item is cited by other documents in WoS
⊙ Detail Information in WoSⓡ Click to see webofscience_button
⊙ Cited 19 items in WoS Click to see citing articles in records_button

qr_code

  • mendeley

    citeulike


rss_1.0 rss_2.0 atom_1.0