Multiple graph embeddings into a processor array with spanning buses

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dc.contributor.authorKim, SYko
dc.contributor.authorChwa, Kyung Yongko
dc.date.accessioned2013-02-28T05:06:30Z-
dc.date.available2013-02-28T05:06:30Z-
dc.date.created2012-02-06-
dc.date.created2012-02-06-
dc.date.issued1998-07-
dc.identifier.citationJOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING, v.52, no.1, pp.24 - 39-
dc.identifier.issn0743-7315-
dc.identifier.urihttp://hdl.handle.net/10203/72914-
dc.description.abstractA processor array with spanning buses (PASB) is a well-known, versatile parallel architecture. A PASB is obtained from a two-dimensional mesh by replacing each linear connection with a bus. In this paper, we show how to optimally embed multiple copies of a graph into a PASB by a labeling strategy. Our embeddings simultaneously achieve an optimal expansion, congestion, and alignment cost. First, we propose a labeling scheme for an N-node graph G, possibly disconnected, such that this labeling makes it possible to optimally embed multiple copies of G into an N' xN' PASB where N' is divisible by N. Second, we show that many important classes of graphs admit this labeling: for example, tree, cycle, mesh of trees, and product graphs such as mesh, torus, or hypercube. Finally, we show how to optimally embed multiple copies of a graph into a multidimensional and possibly nonsquare PASB. (C) 1998 Academic Press, Inc.-
dc.languageEnglish-
dc.publisherACADEMIC PRESS INC-
dc.subjectINTERCONNECTION NETWORKS-
dc.subjectHYPERCUBE-
dc.titleMultiple graph embeddings into a processor array with spanning buses-
dc.typeArticle-
dc.identifier.wosid000075476800002-
dc.identifier.scopusid2-s2.0-0040088476-
dc.type.rimsART-
dc.citation.volume52-
dc.citation.issue1-
dc.citation.beginningpage24-
dc.citation.endingpage39-
dc.citation.publicationnameJOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING-
dc.identifier.doi10.1006/jpdc.1998.1467-
dc.contributor.localauthorChwa, Kyung Yong-
dc.contributor.nonIdAuthorKim, SY-
dc.type.journalArticleArticle-
dc.subject.keywordAuthorgraph embedding-
dc.subject.keywordAuthorprocessor array with spanning buses-
dc.subject.keywordAuthoralignment cost-
dc.subject.keywordAuthorcongestion-
dc.subject.keywordAuthorexpansion-
dc.subject.keywordPlusINTERCONNECTION NETWORKS-
dc.subject.keywordPlusHYPERCUBE-
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