DC Field | Value | Language |
---|---|---|
dc.contributor.author | Kim, SY | ko |
dc.contributor.author | Chwa, Kyung Yong | ko |
dc.date.accessioned | 2013-02-28T05:06:30Z | - |
dc.date.available | 2013-02-28T05:06:30Z | - |
dc.date.created | 2012-02-06 | - |
dc.date.created | 2012-02-06 | - |
dc.date.issued | 1998-07 | - |
dc.identifier.citation | JOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING, v.52, no.1, pp.24 - 39 | - |
dc.identifier.issn | 0743-7315 | - |
dc.identifier.uri | http://hdl.handle.net/10203/72914 | - |
dc.description.abstract | A processor array with spanning buses (PASB) is a well-known, versatile parallel architecture. A PASB is obtained from a two-dimensional mesh by replacing each linear connection with a bus. In this paper, we show how to optimally embed multiple copies of a graph into a PASB by a labeling strategy. Our embeddings simultaneously achieve an optimal expansion, congestion, and alignment cost. First, we propose a labeling scheme for an N-node graph G, possibly disconnected, such that this labeling makes it possible to optimally embed multiple copies of G into an N' xN' PASB where N' is divisible by N. Second, we show that many important classes of graphs admit this labeling: for example, tree, cycle, mesh of trees, and product graphs such as mesh, torus, or hypercube. Finally, we show how to optimally embed multiple copies of a graph into a multidimensional and possibly nonsquare PASB. (C) 1998 Academic Press, Inc. | - |
dc.language | English | - |
dc.publisher | ACADEMIC PRESS INC | - |
dc.subject | INTERCONNECTION NETWORKS | - |
dc.subject | HYPERCUBE | - |
dc.title | Multiple graph embeddings into a processor array with spanning buses | - |
dc.type | Article | - |
dc.identifier.wosid | 000075476800002 | - |
dc.identifier.scopusid | 2-s2.0-0040088476 | - |
dc.type.rims | ART | - |
dc.citation.volume | 52 | - |
dc.citation.issue | 1 | - |
dc.citation.beginningpage | 24 | - |
dc.citation.endingpage | 39 | - |
dc.citation.publicationname | JOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING | - |
dc.identifier.doi | 10.1006/jpdc.1998.1467 | - |
dc.contributor.localauthor | Chwa, Kyung Yong | - |
dc.contributor.nonIdAuthor | Kim, SY | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | graph embedding | - |
dc.subject.keywordAuthor | processor array with spanning buses | - |
dc.subject.keywordAuthor | alignment cost | - |
dc.subject.keywordAuthor | congestion | - |
dc.subject.keywordAuthor | expansion | - |
dc.subject.keywordPlus | INTERCONNECTION NETWORKS | - |
dc.subject.keywordPlus | HYPERCUBE | - |
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