Multiple graph embeddings into a processor array with spanning buses

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A processor array with spanning buses (PASB) is a well-known, versatile parallel architecture. A PASB is obtained from a two-dimensional mesh by replacing each linear connection with a bus. In this paper, we show how to optimally embed multiple copies of a graph into a PASB by a labeling strategy. Our embeddings simultaneously achieve an optimal expansion, congestion, and alignment cost. First, we propose a labeling scheme for an N-node graph G, possibly disconnected, such that this labeling makes it possible to optimally embed multiple copies of G into an N' xN' PASB where N' is divisible by N. Second, we show that many important classes of graphs admit this labeling: for example, tree, cycle, mesh of trees, and product graphs such as mesh, torus, or hypercube. Finally, we show how to optimally embed multiple copies of a graph into a multidimensional and possibly nonsquare PASB. (C) 1998 Academic Press, Inc.
Publisher
ACADEMIC PRESS INC
Issue Date
1998-07
Language
English
Article Type
Article
Keywords

INTERCONNECTION NETWORKS; HYPERCUBE

Citation

JOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING, v.52, no.1, pp.24 - 39

ISSN
0743-7315
DOI
10.1006/jpdc.1998.1467
URI
http://hdl.handle.net/10203/72914
Appears in Collection
CS-Journal Papers(저널논문)
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