Evaluation of double spacer local oxidation of silicon (LOCOS) isolation process for sub-quarter micron design rule

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Double Spacer local oxidation of silicon (LOCOS) with shallow recess of silicon (DS-LOCOS) is described. The process has two spacers, a thin nitride spacer and a medium temperature chemical vapor deposition (CVD) oxide spacer. The process does not have intentional silicon recess etching step but achieves the shallow recess of silicon through nitride overetchings. It has been found that the key processes of the DS-LOCOS are both isolation etching and spacer etching, which critically affect 2 Delta W and V-t roll-off behaviors of active transistor and junction characteristics. The DS-LOCOS achieves physical bird's beak length of below 0.03 mu m/side, field oxide volume ratio over 80%, and superior planar surface. The DS-LOCOS also gives no degradation in punchthrough voltage down to 0.20 mu m isolation spacing and in gate oxide reliability. These results show that the DS-LOCOS is a simple and promising isolation technology for sub-quarter micron design rule.
Publisher
JAPAN J APPLIED PHYSICS
Issue Date
1997-03
Language
English
Article Type
Article; Proceedings Paper
Citation

JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES REVIEW PAPERS, v.36, no.3B, pp.1433 - 1438

ISSN
0021-4922
DOI
10.1143/JJAP.36.1433
URI
http://hdl.handle.net/10203/71184
Appears in Collection
EE-Journal Papers(저널논문)
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