Qos aware mapping of cores onto NoC architectures

Abstract

The trend of integration of many IP blocks in a single chip has driven the evolution of on-chip communication``s architecture. The de-vice feature size is continuously shrinking and the traditional bus-based architectures will not be able to meet the requirements of System-on-Chip (SoC) implementation. An on-chip packet switched network or Networks-on-Chip (NoCs) have been recently proposed as a promising solution to future SoC communication problems. The NoC, somewhat, resembles the parallel computer network. However, the NoC design highly requires the certain satisfaction of latency, power consumption, and area constraints. The latency of the network relates much to throughput and power consumption. Moreover, the IPs and the network are heterogeneous. Hence, a certain mapping of IPs onto a certain architecture produces a certain value of network latency as well as power consumption. The change of mapping scheme leads to a significant change of the values of these constraints. The fact that if we want to maximize the system``s throughput, the network latency is also increase and if we minimize the network latency, the trade off is that the throughput will decrease. In this thesis, we first present an mapping scheme that does compromise between throughput maximization and latency minimization. This sub-optimal mapping is found using the spanning tree searching algorithm. Then we assess the adaptive routing behavior on on-chip network. This routing algorithm is able to achieve much higher saturation throughput that is nearly 20% in our simulation and lower average packet latency compared to using deterministic routing. The experiment architecture using here is Mesh based topology. We use NS2 to simulate the system throughput and system power consumption is calculated using Orion model.