The CMOS technologies have become increasingly attractive for use in wireless receivers and it might have been expected to do that in the future. Also, among all RF blocks, voltage-controlled oscillator (VCO) has received the most attention in recent years. Therefore, it is a good challenge to design for the high performance VCO on the CMOS chip. In this thesis, we present the low power Quadrature VCO applied to down-mixer of the receiver system by using the CMOS technology.
In this paper, a new quadrature VCO (QVCO) topology is proposed where the back-gates of the core transistors are used as coupling terminals. The use of back-gates reduces the power dissipation and removes the additional noise contributions compare to the conventional coupling transistor based topology. The advantages of the proposed QVCO topology in comparison with prior works are exploited based on simulation. A QVCO based on the proposed topology with additional design ideas has been implemented using a 0.18-$\mum$ CMOS technology for 1 GHz-band operation, and measurement shows the phase noise of -120dBc/Hz at 1MHz offset with output power of 2.8dBm, while dissipating only 3mA for the whole QVCO from 1.8V supply.
Additionally, a 5-GHz LNA for wireless LAN application based on 0.5$\mum$ SiGe BiCMOS is explained in Appendix A.