CMOS I/Q demodulator design for the IEEE 802.11a direct-conversion receiver

Abstract

A direct-conversion I/Q demodulator for IEEE 802.11a applications is designed using 0.25-um CMOS process. In this paper, a flicker noise reduction method is suggested. And the average noise figure improvement is larger than 5.7 dB. The principal of this method is to reduce the capacitance at the source node of the switching stages. The designed I/Q demodulator is composed of 2 double-balanced down-conversion mixer and 4 IF buffer. Simulation result show voltage conversion gain = 11.8dB, input-referred 1-dB compression point = -1.2dBm, average noise figure in the signal band = 12dB, input-referred IP2 = +43 dBm respectively, at 3V supply voltage, and 4.2mA current consumption for each mixer. And LO to IF isolation and LO to RF isolation is 66 dB and 88 dB.