A digital front-end receiver design which is composed of I/Q mismatch compensator and channel selection filter for DVB-T application is introduced in this thesis.
One reported I/Q mismatch compensator with best image rejection ratio (65dB) and simple hardware is extended to have fast adaptation speed as well by adopting adaptive step-size for LMS-based zero-forcing sign detection algorithm. The proposed I/Q mismatch compensator shows nine times faster adaptation speed as well as image rejection ratio still remains high. One deficit that the compensation algorithm fails in case of DC offset existence is cleared by placing DC offset compensator in advance of I/Q mismatch compensator. BER simulation satisfies SNR requirement for specific condition of DVB-T application.
Digital channel selection filters of 6/7/8MHz bandwidth are designed to have 45dB adjacent channel attenuation. Parks-McClellan algorithm designs 47/47/46-tap FIR filters and the designed filters are converted as hardware by verilog. The functionality of verilog-coded hardware is verified with that of simulation.