A study on hardware of MAP decoder for CDMA2000 turbo code

Abstract

In this paper, this thesis introduces the MAP decoder model for turbo code in cdma2000 specification, and the MAP decoder optimization used by the force-directed scheduling algorithms. We can compare the Pietrobon’s MAP decoder with the modified MAP decoder. The first, the modified MAP decoder structure have not the BM memory, therefore 245k($12282\times4\times5$) memory remove and N(frame size) time reduce. The second, we can choose the Max-log MAP method. This method decrease the coding gain by 0.3dB, but hardware complexity reduce. The third, the FSMC and the RSMC have the ACS of parallel type. Therefore, we can have only 2 clock for FSMC. The fourth, we can choose the BRSM memory, therefore the BFSMC and the BRSMC is operated the same time, and then as the FSMC memory(or the RSMC memory) is filled, the LLR operation is completed. The modified MAP decoder is shown 1.5 times as fast as the Pietrobon’s MAP decoder.