Heuristics for scheduling burn-in operations in a semiconductor test facility to minimize total tardiness = 반도체 제조 공정 중 번인 공정에서의 납기를 고려한 스케줄링 알고리듬 개발

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dc.contributor.advisorKim, Yeong-Dae-
dc.contributor.advisor김영대-
dc.contributor.authorLee, Kyoung-Eun-
dc.contributor.author이경은-
dc.date.accessioned2011-12-14T04:07:44Z-
dc.date.available2011-12-14T04:07:44Z-
dc.date.issued2005-
dc.identifier.urihttp://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=244205&flag=dissertation-
dc.identifier.urihttp://hdl.handle.net/10203/40721-
dc.description학위논문(석사) - 한국과학기술원 : 산업공학과, 2005.2, [ iii, 54 p. ]-
dc.description.abstractIn this thesis, we consider a scheduling problem in a semiconductor test facility, in which tardiness of orders is to be minimized. We focus on the loading/unloading workstation and the burn-in workstation, which may be considered bottleneck workstations in the test facility. In the loading/ unloading workstation, there are unrelated parallel machines, while there are identical parallel batch-processing machines called chambers in the burn-in workstation. Each chamber can process up to B boards simultaneously. A set of wafers is loaded on a board in the loading workstation, before a set of boards can be processed together in the burn-in workstation. We present four types of heuristic algorithms for scheduling problems in the burn-in workstations: extended list scheduling algorithms; look-ahead list scheduling algorithms; algorithms based on an existing heuristic developed for a single machine tardiness problem; and local search algorithms. Also, we develop several algorithms for the loading/unloading workstations. To evaluate performance of the algorithms, a series of computational experiments are performed on randomly generated test problems and results show that the suggested heuristic algorithms work well and outperform the existing rule currently used in a real system.eng
dc.languageeng-
dc.publisher한국과학기술원-
dc.subjectburn-in operations-
dc.subjecttotal tardiness-
dc.subjectscheduling-
dc.subjectHeuristic-
dc.subjectsemiconductor-
dc.subject반도체-
dc.subject번인 공정-
dc.subject총납기지연-
dc.subject스케줄링-
dc.subject휴리스틱-
dc.titleHeuristics for scheduling burn-in operations in a semiconductor test facility to minimize total tardiness = 반도체 제조 공정 중 번인 공정에서의 납기를 고려한 스케줄링 알고리듬 개발-
dc.typeThesis(Master)-
dc.identifier.CNRN244205/325007 -
dc.description.department한국과학기술원 : 산업공학과, -
dc.identifier.uid020033424-
dc.contributor.localauthorKim, Yeong-Dae-
dc.contributor.localauthor김영대-
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