Due-date based algorithm for order-lot pegging in a semiconductor wafer fabrication Facility반도체 생산 공정에서 납기를 고려한 오더-랏 결합 방법에 관한 연구

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This thesis focuses on a pegging problem or an order-lot assignment problem in a semiconductor wafer fabrication facility. Pegging is a process of assigning each lot to an order. In general, there are two types of pegging policies used in semiconductor manufacturing systems: hard pegging policy and soft pegging policy. Under the hard pegging policy, lots are assigned to an order and the lot-order assignment is maintained until the order and lots are completed. On the other hand, under the soft pegging policy, the lot-order assignment can be modified while they are being processed. We develop new pegging algorithms for the soft pegging policy for the objective of minimizing the number of tardy orders. To evaluate these proposed algorithms, we perform simulation experiments using randomly generated data. Results of the simulation tests show that the new algorithms for the soft pegging policy work better than an existing algorithm as well as the hard pegging policy.
Advisors
Kim, Yeong-Daeresearcher김영대researcher
Description
한국과학기술원 : 산업공학과,
Publisher
한국과학기술원
Issue Date
2005
Identifier
243612/325007  / 020033358
Language
eng
Description

학위논문(석사) - 한국과학기술원 : 산업공학과, 2005.2, [ [ii], 35 p. ]

Keywords

semiconductor fabrication information structureion of g-Hydroxy-cis-Alkenesumina on; order-lot pegging; Total tardiness; the flow analysis of 100W-stack; 정보 구조 ?입체선택적인 요오드고리화 반응에 관한 연구?발광 물질; 진동수준형; 총 납기 지연; 오더-랏; 반도체 생산 공정

URI
http://hdl.handle.net/10203/40705
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=243612&flag=dissertation
Appears in Collection
IE-Theses_Master(석사논문)
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