Highly linear CMOS low noise amplifier

Abstract

A high Linear technique for the (CMOS) low noise Amplifier (LNA) is presented, the proposed method uses an additional PMOS transistor for in-creasing the third order inter modulation distortion (IMD3) current, which generated by the CS and CG stages, but gain and noise is trade-off, but not much, this technique is applied to achieve the linearity of CMOS LNA using 0.18 μm technology. The LNA achieved +14 dBm IIP3, 12dB gain, and 1.2dB NF at 2.4 GHz consuming 8.2 mA from 1.8 V supply.