Register transfer level language(RTLL) simulator for VLSI design

Abstract

As our ability to fabricate complex chips is developed, it is outrunning our ability to design them. As a result, it takes much time to design complex chips. To reduce design time and efforts, many kinds of design assistant tools are under development. We define hardware description language in order to digital hardware. The language is register transfer level language(RTLL). We can describe digital hardwares by means of RTLL. This new language was motivated by the need to efficiently describe invocation of standard-cell. We developed RTLL simulator for simulation of the RTLL description. This paper is on RTLL and RTLL simulator to develop the synthesis method of digital system from register transfer level description. We use the RTLL simulator to check the operation of register level description.