Reference multiplied PLL and phase filtered harmonic locking for low noise frequency synthesizer

Abstract

This thesis presents several architecture which improve the phase noise performance of frequency synthesizer. To decrease the phase noise of frequency synthesizer which is based on phase locked loop(PLL), reference frequency multiplying technique is used. Three architectures are described to implement the idea. First is to use multi-phase injection locked oscillator(ILO). By using multi-phase ILO, phase errors were compared 8 times within a reference frequency. To use both negative edge and positive edge of the reference signal, reference doubler and differential divider output is proposed. These architectures can reduce the phase noise from both charge pump and $\Delta - \Sigma$ modulator noise at the same time. The simulation results shows that proposed architecture has a good phase noise reduction performance. In addition, direct frequency synthesizer is proposed. This architecture can overcome the disadvantages of direct digital frequency synthesizer(DDFS) by using phase filter and injection locking oscillator. These architectures were implemented in $0.13 \mu m$ CMOS process.