HLS-pg: high-level synthesis of power-gated circuits

Abstract

One inherent problem of designing power-gated circuits is the implementation overhead required to support the state retention storage to preserve the circuit execution state in standby mode. It is known that reducing the size of retention storage is the most influential factor for minimizing the loss of the benefit (i.e. power saving) obtained from the application of power gating to circuits. However, the possibilities of reducing the size of retention storage in the logic synthesis or physical design stage are quite limited since restructuring the circuit structure may greatly change or violate many other design parameters that have already been optimized. In this thesis, we address a new problem of high-level synthesis with the objective of minimizing the size of retention storage to be used in the power-gated circuits. Specifically, we propose a complete design framework, called HLS-pg, that starts from the power gating aware-scheduling, allocation, and controller synthesis down to the final circuit layout. The key contribution of the thesis is to solve the power gating-aware scheduling problem, namely, scheduling operations that minimizes the number of retention registers required at the (power gating) control step, while satisfying the resource and latency constraints. From experimentation with benchmark designs using 65-nm technology, it is shown that HLS-pg generates circuits with 27% less leakage current, even with 6% less circuit area and wirelength, compared to the power-gated circuits produced by conventional method.